Title:
CLOCK SIGNAL GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3048960
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To generate a clock signal synchronized with a binarized signal having the non-fixed length of one bit provided by FSK demodulation by providing a binary counting means having a specified function.
SOLUTION: A binary count means 62 counts decimal values from '1' to '7' corresponding to a semicyclic pulse signal bothedg. When the count value is '2' or '3' and the rise and fall of demodulated signal (binarized signal) bidata are detected by an edge detecting means 61 and when the count value is '4' and the rise is detected, the binary count means stops count-up once. When the count is '4' and the fall is detected and when the count value is '5' or '6' and the rise or the fall is detected, the count value is counted up for +2. The output of binary count means 62 from the minimum bit to the 3rd bit is outputted as the clock signal.
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Inventors:
Akira Shimojima
Application Number:
JP14035297A
Publication Date:
June 05, 2000
Filing Date:
May 29, 1997
Export Citation:
Assignee:
TAIYO YUDEN CO.,LTD.
International Classes:
G11B20/14; H03M5/12; H04L7/00; H04L7/02; H04L27/14; (IPC1-7): H04L27/14; G11B20/14
Domestic Patent References:
| JP6188922A | ||||
| JP983584A | ||||
| JP10336256A |
Attorney, Agent or Firm:
Seiko Yoshida