PURPOSE: To generate a stable clock signal even with the reception of a synchronizing signal including defects, by storing a bit synchronizing signal appeared at the head of a transmitted digital signal in a shift register with the output pulse of a quartz oscillator and comparing the internal bits.

CONSTITUTION: When synchronizing signals of 1, 0, 1, 0... appeared at the head of an input digital signal are inputted to a terminal 1, a gate 3 is set and the signals are stored in a shift register 4 in order with a shift pulse generated at a quartz oscillator 5. A frequency F of the oscillator 5 is set as the product between an integer (n) and a bit rate Br, F=n.Br and 2m-bit's share of the input signal is stored in the register 4, by setting the number M of storage elements of the register 4 as 2mn(where; m is an integer). Since the content of storage of elements apart by n bits each is all "1" or "0" at normal state, according to the bit synchronizing signals (1010...), even if there are missing bits due to noises, the decision by majority is taken at a correction circuit 6 to correct the missing. The output is differentiated at a differentiation circuit 7 to reset a counter 8 counting the output of the quartz oscillator 5 and to obtain a clock signal 4.