To solve the problem, wherein there is a probability that a clock signal generation circuit outputs output clock, in a state where the phase differences among the clock signals are shifted by 180 degrees (a pseudo-locked state) from a locked state.
A clock signal generation circuit of a delay-locked loop type is provided, including (a) delay line configured to delay a first clock signal to generate a second clock signal; (b) a delay amount controller, configured to perform variable control of the amount of delay in the delay line, such that the phase of the second clock signal is in synchronization with the phase of the first clock signal; (c) a pseudo-lock detecting section, configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and (d) a pseudo-locked state release section, configured to change the amount of delay in the delay line, when pseudo-locked state is detected.
MIZUHASHI HIROSHI
KOIDE HAJIME
