To make it possible to set the frequency-division rate of each clock signal, and to switch the frequency-division rate of the clock signal based on the set frequency-division rate to output a clock signal in a clock generation circuit for generating a plurality of clock signals and a semiconductor integrated circuit.
This clock signal generation circuit is provided with a PLL circuit 21 for generating a reference clock signal CK0; frequency-division circuits 22 and 23 for frequency-dividing the reference clock signal CLK0, and for outputting clock signals CK1 and CK2; frequency-division rate setting registers 24 and 25 for storing different frequency-division rates in those respective frequency-division circuits 22 and 23; and a frequency-division rate switching part 26 for switching the frequency-division rates in the frequency-division circuits 22 and 23 into the frequency-division rates set in the frequency-division rate setting registers 24 and 25 synchronously with the reference clock signal CK0.
KURASE HIROYUKI
FUNAMOTO KENJI
| JPS63292312A | 1988-11-29 | |||
| JPH06342415A | 1994-12-13 | |||
| JPH09282042A | 1997-10-31 | |||
| JP2003108433A | 2003-04-11 | |||
| JP2004180078A | 2004-06-24 | |||
| JP2001051747A | 2001-02-23 | |||
| JPH06290281A | 1994-10-18 | |||
| JP2001014213A | 2001-01-19 |
Go Sakuma