To improve accuracy of a clock signal.

A clock signal generation device includes processing sections 31 to 33 for performing correction processing to increase/decrease a first error being a differential value between the first number of counting times of a pulse signal S2 and a frequency of the pulse signal S2 between output points of time of one second signal S1 for two times from the determined number of times when a clock signal S3 is generated every time the pulse signal S2 is counted by the determined number of times. Each processing section specifies the second number of counting times as a second error when the second number of counting times of the pulse signal S2 during time from the output point of time of the one second signal S1 to an output point of time of a one second completion signal S6 outputted every time the number of clock signals S3 to be generated for one second is generated is a first specified value or below. When the second number of counting times is larger than the first specified value and an absolute value of a differential value between a value obtained by adding the value of the frequency and the first error, and the second number of counting times is the first specified value or below, the differential value is specified as a third error. In the correction processing, the total value of the first to third errors is increased/decreased from the determined number of times.