Title:
CLOCK SIGNAL GENERATOR USING FREQUENCY FRACTION DIVISION
Document Type and Number:
Japanese Patent JPH0514185
Kind Code:
A
Abstract:
PURPOSE: To form a clock signal with less phase shift and amplitude fluctuation with simple and small constitution by generating the clock signal through a pulse subtracter and a dividing unit, which are controlled by an accumulation means. CONSTITUTION: A signal R with a specified period generates a frequency divided clock Ck with a frequency which is a divisor of the frequency of the signal R by being processed in a pulse subtracter 1 and a dividing unit 2. At that time, the clock Ck is supplied to the accumulation means 2 provided with an addition circuit 31 and a register 32. Whenever the product of the fractional part of the clock Ck and the number of pulses of the signal Ck counted from the starting time changes by one unit by which the integer part of the signal Ck increases by one, the subtracter 1 is triggered. Thus, a clock signal generator using frequency division for forming the clock signal with less phase shift and amplitude fluctuation is obtained with simple and small constitution.
Inventors:
RIYUTSUKU DARUTOWA
PEETERU RUUSENSU
ETEIENNU BANJIIREHEN
PEETERU RUUSENSU
ETEIENNU BANJIIREHEN
Application Number:
JP23744791A
Publication Date:
January 22, 1993
Filing Date:
August 23, 1991
Export Citation:
Assignee:
ALCATEL RADIOTELEPHONE
International Classes:
H03K23/64; H03K23/66; (IPC1-7): H03K23/64
Attorney, Agent or Firm:
Yoshio Kawaguchi (3 outside)
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