PURPOSE: To obtain a filter circuit having a high performance by controlling a timing between P and N channel MOS transistors by a timing circuit, and feeding back an output signal of the filter circuit to a timing control circuit, in a clock signal supply device of a switched capacitor filter circuit.

CONSTITUTION: In a switched capacitor filter (CMOS.SCF) circuit 2 provided between a signal input terminal 1 and a signal output terminal 3, a CMOS switch consisting of P and N transistors is contained, and it is opened and closed by clock signals from a first SCF clock signal line 9 and a second SCF clock signal line 10. To a feedback amplifier 4, an output signal of the circuit 2 is inputted and its output terminal is connected to an input terminal of a timing control circuit 8 through a signal line 5, and the circuit 8 controls a timing of the clock signals applied to first and second clock input terminals 6, 7, in accordance with an output signal of the amplifier 4. Thereafter, this control result is outputted to the signal line 9 and 10.