Title:
CLOCK SIGNAL SUPPLY METHOD
Document Type and Number:
Japanese Patent JP2540762
Kind Code:
B2
Abstract:
PURPOSE: To suppress the variance of wiring lengths using a simple method by sorting all clock input nodes of function blocks into a finite number of groups based on a specific sorting method.
CONSTITUTION: The flip-flops FF 3 are sorted into a finite number of groups based on such a sorting method that can decide that the density distributions are uniform in an area where the relevant group of FFs 3 is apparently included and also equal to each other. The FFs 3 existing close to each other in terms of space and belonging to the same group are gathered and grouped. For instance, the FFs 3 of an area 2 are sorted every four pieces into the FFs 4 of a 1st group, the FFs 5 of a 2nd group, and the FFs 6 of a 3rd group. So that an even FF density distribution is attained. One of clock buffers 7-9 is placed at the arithmetic average position of coordinates of the FFs 3 of each group. Then the output nodes of buffers 7-9 are wired individually to the clock input nodes of FFs 3 included in the corresponding group.
Inventors:
MATSUMOTO HIROSHI
Application Number:
JP28099693A
Publication Date:
October 09, 1996
Filing Date:
November 10, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F1/10; G06F17/50; H01L21/82; H03K5/15; (IPC1-7): G06F1/10; G06F17/50; H01L21/82
Domestic Patent References:
| JP561564A | ||||
| JP5233092A | ||||
| JP588776A | ||||
| JP5159080A | ||||
| JP476610A | ||||
| JP2240712A | ||||
| JP293917A | ||||
| JP2134919A | ||||
| JP1157115A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)