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Title:
CLOCK SIGNAL VARIABLE DEVICE
Document Type and Number:
Japanese Patent JPH04207524
Kind Code:
A
Abstract:

PURPOSE: To facilitate digital IC processing and miniaturization with less jitter by providing a reference clock generating circuit, a switch circuit, a frequency divider circuit, a counter circuit and a preset data output circuit on the variable device.

CONSTITUTION: Since a control signal GS from a counter circuit 23 makes a switch circuit 22 nonconductive for a prescribed period decided by a preset data PSO, the switch circuit 22 extracts a prescribed number of reference clock signal pulses CKST. The degree of a change in the clock signal CKT outputted from the switch circuit 22 is adjusted depending on the extracted pulse number. Since the clock signal is changed without using a voltage controlled oscillator(VCO), jitter is reduced and digital IC processing and miniaturization are facilitated.


Inventors:
NAKANE HIROSHI
Application Number:
JP33560990A
Publication Date:
July 29, 1992
Filing Date:
November 30, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11B20/10; H03K23/64; H03L7/00; (IPC1-7): G11B20/10; H03K23/64; H03L7/00
Attorney, Agent or Firm:
Saichi Suyama



 
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