Title:
CLOCK SUPPLY CIRCUIT
Document Type and Number:
Japanese Patent JP3732556
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve considerably a clock skew between a signal via a through- path and a frequency divided signal via a frequency divided path from a same clock signal source in the clock supply circuit.
SOLUTION: The circuit is provided with a clock signal source 10, a frequency divided path 11a that subjects a clock signal received from the clock signal source 10 to frequency division by a frequency divider circuit 11 consisting of a binary counter using a D flip-flop circuit and giving the resulting signal to a controlled circuit 90 and a through-path 12a through which the clock signal received from the clock signal source 10 is passed to a dummy circuit 12 with a signal delay equal to a signal delay of the frequency divider circuit without subjecting the received clock signal to frequency division and providing the resulting signal to the controlled circuit 90.
Inventors:
Shinichi Osera
Yukihiro Saeki
Yukihiro Saeki
Application Number:
JP19045695A
Publication Date:
January 05, 2006
Filing Date:
July 26, 1995
Export Citation:
Assignee:
Toshiba Microelectronics Co., Ltd.
Toshiba Corporation
Toshiba Corporation
International Classes:
H03K5/00; H03K5/15; H03K21/08; (IPC1-7): H03K5/00; //H03K21/08
Domestic Patent References:
| JP642417A | ||||
| JP6310914A | ||||
| JP2237215A | ||||
| JP8335859A |
Attorney, Agent or Firm:
Takehiko Suzue
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