PURPOSE: To simplify the circuit and to reduce cost by operating a microcomputer core synchronously with a reset terminal for system initialization.

CONSTITUTION: When a signal having polarity to initialize a microcomputer core 1 is inputted to a reset terminal 4 for initializing the system, the reset of a counter 8 is released, and the microcomputer core 1 is reset. At such a time, clocks are successively supplied from a clock supply terminal 3 and after a frequency divided output 5 from a frequency divider circuit 7 executes toggle operations, an output 6 of the counter 8 is made active. Then, the frequency divider circuit 7 is initialized and fixed at a low level. Next, when a signal having a polarity reverse to the initialization of the microcomputer core 1 is inputted to the reset terminal 4, the reset of the microcomputer core 1 is released, the counter 8 is initialized, the output 6 of the counter 8 is made inactive, the frequency divider circuit 7 starts the frequency dividing operation, and the frequency divided output 5 executes the toggle operations.