To increase a clock frequency by compensating a propagation delay that is generated especially by clock wiring.

A delay compensation PLL circuit 4 is provided at each input part of a plurality of those that receive clocks from a clock generator 1, and at the same time, the clock generator 1 is connected to the delay compensation PLL circuit 4 by clock wiring 3. A delay detector/delay setting instrument 7 is provided to measure the delay time of the clock signal that is generated by the clock wiring 3 during system reset periods and to advance the phase in the delay compensation PLL circuit 4 based on the measured delay time.