Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CLOCK SUPPLYING DEVICE TO SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06338590
Kind Code:
A
Abstract:

PURPOSE: To ease clock skew by providing clock receiving lines, which are provided so as to surround functional block regions with respect to each one functional block, are connected to a clock distributing line and form the clock input terminals of the functional blocks.

CONSTITUTION: A ring-shaped clock receiving line is formed so as to surround the outer surface of each functional block 3. A clock distributing line 11, which connects a clock buffer 1 and each functional block 3, is provided. The clock distributing line 11 is extending to the vicinity of the clock receiving line of the functional block 3 in one straight-line shape without any branching from the clock buffer 1 and branched at first in the vicinity. The clock distributing line 11 is connected to the clock receiving lines through the branched lines. Thus, clock skew can be eased, and the CAD wiring becomes easy by the shortened amount of the wiring.


Inventors:
ISHII CHIHIRO
Application Number:
JP12967893A
Publication Date:
December 06, 1994
Filing Date:
May 31, 1993
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA CORP
International Classes:
G06F1/10; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L27/04; G06F1/10; H01L21/82
Attorney, Agent or Firm:
Kazuo Sato (3 others)