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Patent Searching and Data


Title:
CLOCK SYNCHRONIZATION DELAY CONTROL CIRCUIT AND ITS METHOD
Document Type and Number:
Japanese Patent JPH11272355
Kind Code:
A
Abstract:

To make it possible to reduce power consumption in operation at high frequency.

Power supply voltage is impressed to respective unit delay units in a unit delay unit group 61 through a power supply terminal 63 and power supply voltage is impressed from the terminal 63 to respective unit delay units in a unit delay unit group 62 through a power supply controlling switch 65. A forward pulse(FP) detection circuit 64 detects the propagation of an FP from an N step up to a step before the prescribed number of steps and outputs the detected result to the switch 65. Thereby when the FP is propagated to the (N+1)th step, power supply voltage is also supplied to the unit group 62. When the FP is not propagated up to the (N+1)th step, no power is supplied to the unit group 62, so that useless power consumption can be suppressed.


Inventors:
KAMOSHITA MASAHIRO
TODA HARUKI
FUSE TSUNEAKI
OWAKI YUKITO
Application Number:
JP6906098A
Publication Date:
October 08, 1999
Filing Date:
March 18, 1998
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F1/04; G06F1/10; G06F1/32; G11C11/4074; G11C11/4076; G11C11/407; H03K5/13; H03K5/131; H04L7/02; (IPC1-7): G06F1/10; G06F1/04; G11C11/407; H03K5/13; H04L7/02
Attorney, Agent or Firm:
Susumu Ito