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Patent Searching and Data


Title:
CLOCK SYNCHRONIZING SYSTEM IN TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JPS6184941
Kind Code:
A
Abstract:

PURPOSE: To attain stable transmission by providing a dead band to phase adjustment of data and a clock in the reproduction of a reception clock at each node to eliminate the clock supply and phase difference adjustment at a specific node.

CONSTITUTION: A reception data changing point detection section 131, a phase comparison section 132 and a clock generating section 133 are provided in a clock synchronizing circuit reproducing a reception clock RXC synchronizing with a reception data RD and the clock RXC adjusted in response to the phase difference θ is outputted. The comparison section 132 detects a phase difference θbetween the data changing point and the clock RXC generated by the generating section 133, which changes the generated frequency (f) by ±Δf around a center value f0 according to the difference θ. Thus, a dead band is provided to the phase synchronizing circuit to absorb the phase difference thereby eliminating the need for the clock supply and phase difference adjustment at the specific node.


Inventors:
NOMI MAKOTO
MIYAMOTO SHOJI
Application Number:
JP20622484A
Publication Date:
April 30, 1986
Filing Date:
October 03, 1984
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04L7/033; H04L12/42; (IPC1-7): H04L11/00
Domestic Patent References:
JPS5619263A1981-02-23
JPS5713838A1982-01-23
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)