Title:
CLOCKED INVERTER CIRCUIT, SHIFT REGISTER, SCANNING LINE DRIVE CIRCUIT, DATA LINE DRIVE CIRCUIT, ELECTROOPTIC APPARATUS, AND ELECTRONIC APPARATUS
Document Type and Number:
Japanese Patent JP2006191264
Kind Code:
A
Abstract:
To provide a clocked inverter to which a delay function is attached.
The clocked inverter 11n is provided with an inversion circuit 20, a first circuit 21, and a second circuit 22. When the first and second circuits 21, 22 are active, power is supplied to the inversion circuit 20, and the clocked inverter 11n is activated. The first circuit 21 is provided with first and second transistors TRr1, Tr2 connected in series, and a delay circuit tdn. The second transistor Tr2 is controlled by an inverted clock signal and the 1st transistor Tr2 is controlled by an inverted clock signal delayed by the delay circuit tdn. Thus, the ON/OFF state of the first circuit 21 is controlled by delaying only a rising edge of the inverted clock signal.
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Inventors:
KATAYAMA SHIGENORI
Application Number:
JP2005000424A
Publication Date:
July 20, 2006
Filing Date:
January 05, 2005
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H03K5/135; G02F1/133; G09G3/20; G09G3/36; G11C19/00; H03K19/096; H03K23/54
Attorney, Agent or Firm:
Masahiko Ueyanagi
Fujitsuna Hideyoshi
Osamu Suzawa
Fujitsuna Hideyoshi
Osamu Suzawa