PURPOSE: To attain the assured detection of a CMI code error by holding the levels of word bits of the first and second halves of a CMI signal by different holding circuits and processing the outputs of both holding circuits with various types of logical circuits and error detecting circuits.

CONSTITUTION: The word bits of the first and second halves of a signal CMI are held by holding circuits 10 and 11 respectively and the synchronization is secured between both output signals A and B of circuits 10 and 11. A logical circuit consisting of an inverter 12 and an OR gate 13 detects 0 of the signal A or 1 of the signal B. Then a signal G is produced and supplied to a logical circuit 14. The circuit 14 converts the signal G into a pulse for each cycle of a clock and delivers a signal H to a logical circuit 15. The circuit 15 transmits the signal H only when the output signal I of an error detecting circuit 17 is set at 0 and supplies a signal J to a logical circuit 16. The circuit 16 inverts its output with each input of the signal J and supplies the signal K synchronous with the signals following the signals A and B by a word to the circuit 17. The circuit 17 delivers a signal I only when the coincidence is secured among signals A, B and K. Then an error detecting circuit 18 delivers a signal L via a logical circuit 19 when 0 of the signal A and 1 of the signal B are detected.