To provide a CML latch circuit which is operated even with power supply voltage lower than conventional power supply voltage.

Between a power supply line 160 and a ground line 170, resistors 110, 111, first and second nMOS transistors 100, 101 and a current source nMOS transistor 150 are connected, pMOS transistors 102, 103 and resistors 121, 120 are connected to a drain of the transistor 101, and pMOS transistors 104, 105 of a cross couple are connected to a drain of the transistor 100. Thus, the four pMOS transistors perform latch operations and further, the number of elements connected between the power supply line 160 and the ground line 170 is reduced. Thus, the CML latch circuit is operated even with the low voltage.