Title:
CMOS CIRCUIT FOR CONVETING TERNARY SIGNAL TO BINARY SIGNAL
Document Type and Number:
Japanese Patent JPS5541093
Kind Code:
A
Abstract:
The ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs. By further addition of a NAND or a NOR gate the circuit can be used in an integrated circuit as option releasing stage without additional terminal for the option signal which has only to be chosen as the middle value of the ternary signal whereas its lower and upper values are the binary signals.
Inventors:
BORUFUGANGU GORINGAA
YOOAHIMU GUROOSE
ARUNORUDO UURENHOFU
YOOAHIMU GUROOSE
ARUNORUDO UURENHOFU
Application Number:
JP11680879A
Publication Date:
March 22, 1980
Filing Date:
September 13, 1979
Export Citation:
Assignee:
ITT
International Classes:
H03K19/0175; H03K19/0948; H03K19/20; H03M5/16; H04L25/22; H04L25/48; H04L25/49; (IPC1-7): H03K19/00; H04L25/03; H04L25/49
Domestic Patent References:
| JPS5299031A | 1977-08-19 |