To reduce hazard occurrence probability by allowing a buffer memory element that is synchronously with a delayed symmetrical clock signal having a clock width of a low phase to store data synchronously with an asymmetrical clock signal so as to decrease number of switching processes.

A circuit device to generate an asymmetrical clock signal for a buffer memory element is made up of three inverting slave latches LA1-LA3 and a NAND gate UG4. A symmetrical clock signal is given to the inverting slave latches LA1-LA3 which act like delay elements, in which a delayed clock signal CLKD with a clock width of a low phase is produced. Furthermore, the NAND gate UG 4 synchronous with the signal CLKD generates asymmetrical clock signal CLK0. In the case that the buffer memory element is controlled by the clock signal CLK0, a buffer memory element at a final stage does not transfer a data signal to a post-stage connection circuit block before it is not warranted that the buffer memory element at the final stage receives the data signal from a preceding stage circuit block.