PURPOSE: To decrease the number of elements by providing a transmit gate consisting of a (p) or (n) channel MOSFET and a latch circuit which performs level compensation.

CONSTITUTION: The (p) channel MOSFETQ1 forms the transmit gate which inputs an input signal D to a master latch circuit ML. Similarly, an (n) channel MOSFETQ4 forms a transmit gate which inputs the output signal of the latch circuit ML to a slave latch circuit SL. A clock signal C is applied to the gates of both FETs Q1 and Q4 in common. Each latch circuit ML (SL) consists of an output CMOS inverter IV1 (IV3) and a feedback COMS inverter IV2 (IV4) for level compensation. Thus, the number of elements is decreased.