PURPOSE: To prevent adverse influences on circuits connected on the downstream side by connecting a resistance between the input and earth terminals of each inverter of the final stage and preceding even numbered stages of the final stage among inverters of plural stages and a resistance between the input and power supply terminals of each inverter of preceding odd numbered stages of the final stage.

CONSTITUTION: When power supply is applied and a power supply voltage VCC rises, N-type transistors QN1 and QN3 are always set to turned off states, since their gates are grounded through resistances R1 and R3, and a P-type transistor QP2 is always set to a turned off state, sine its gate is connected to a power supply terminals through a resistance R2. Therefore, it is possible to always maintain the output (node N2) of an inverter 1 at a high level and the output (node N3) of another inverter 2 at a low level and, in addition, the output (node T0) of an inverter 3, namely, an output signal OUT at a high level irrespective of the level of the threshold voltages of each transistor of the inverters 1, 2, and 3.