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Title:
CMOS OPERATIONAL AMPLIFIER
Document Type and Number:
Japanese Patent JPH0541496
Kind Code:
A
Abstract:

PURPOSE: To extremely reduce the power supply noise of an amplifier and, at the same time, to stabilize the operation of a digital-analog mixed integrated circuit by forming a capacitor of the first and second metallic wiring layers facing each other with an interlayer insulating film in between.

CONSTITUTION: A capacitor is formed by facing the first and second metallic wiring layers 2 and 3 with an interlayer insulating film in between. When the capacitor is formed in such way, high-frequency digital noise superimposed upon a power supply voltage line is by-passed from a VDD (positive voltage) to a VSS (negative voltage), because an electrostatic capacity is formed between the VDD and VSS, and the capacitor is formed to the power supply line of an amplifier. Therefore, a measure can be taken against the noise of the amplifier by the conventional two metallic layer wiring technique without changing its process.


Inventors:
KOIDE JIRO
Application Number:
JP19672491A
Publication Date:
February 19, 1993
Filing Date:
August 06, 1991
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L27/092; H01L21/8238; (IPC1-7): H01L27/092
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)



 
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