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Title:
CMOS OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH05335906
Kind Code:
A
Abstract:

PURPOSE: To ensure a sufficient load drive capability while reducing power consumption of an output circuit comprising an operational amplifier.

CONSTITUTION: A P-channel MOS transistor(TR) 5 and an N-channel MOS TR 7 are connected in series between a high potential power supply Vcc and a low potential power supply Vss to form a CMOS output stage. The circuit is provided with a level shift circuit 3 shifting a level of an input signal IN to output the signal to a gate of at least one of the TRs of the CMOS output stage 4, and the level shift circuit 3, which consists of the series connection of a constant current source and a TR whose conduction channel is opposite to the TR of the CMOS output stage 4 connecting to the circuit 3. The input signal IN is inputted to a gate of the TR of the level shift circuit 3 and an output signal is outputted to a gate of the TR of the CMOS output stage 4 from a connecting point between the TR and the current source.


Inventors:
HIROSE MASAHITO
Application Number:
JP13908092A
Publication Date:
December 17, 1993
Filing Date:
May 29, 1992
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
H03K5/02; H03K5/08; H03K17/16; H03M1/66; (IPC1-7): H03K5/02; H03K5/08; H03K17/16; H03M1/66
Attorney, Agent or Firm:
Hironobu Onda



 
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