PURPOSE: To avoid the latch-up of a CMOS.IC by a method wherein the p type layer of an n-MOS transistor is encircled by the n type layer separated from the n well of a p-MOS transistor.
CONSTITUTION: A CMOS inverter circuit is formed in an n type layer 4 separated from the n well of an n-MOS transistor 2. A parasitic pnp transistor 5 comprising positive feedback in a reference CMOS inverter is connected to a parasitic npn transistor 6 through the intermediary of the parasitic npn transistor 7 and the parasitic pnp transistor 8 between p-MOS and n-MOS. At this time, the npn transistor 7 and the pnp transistor 8 whose all terminals are impressed with the inverse bias are prevented from being actuated. Through these procedures, the actuations of positive feedback circuit can be suppressed thereby enabling the latch-up of CMOS.IC to be avoided.
Yumoto attack
Moriguchi Akisada
Koji Kabayama
Kazuyuki Tajiri
