PURPOSE: To reduce the power consumption and increased the speed of a decoder circuit having a CMOS-configurated driver circuit which drives a memory cell, by impressing a signal voltage by which no or very little through electric current flows in the CMOS.

CONSTITUTION: The decoder circuit of this invention is composed of the 1st decoder circuit 2 which selects the 1st signal lines (1-0)W(1-63) by inputting the 1st address signals A0WA5 and a control signal B, the 2nd decoder circuit 4 which selects the 2nd signal lines (3-0)W(3-3) crossing the 1st signal lines by inputting the 2nd address signals A6 and A7 and a control signal CE, a gate circuit at the intersecting point of the two signal lines, and a driver 7 of a CMOS-configuration which drives a memory cell 6. The gate circuit 5 supplies a voltage signal which is almost equal to the supply voltage of the CMOS of the driver circuit 7, so that no through electric current flows in the CMOS. Therefore, the electric current to be consumed is reduced.