PURPOSE: To suppress increase of number of circuit elements and save power consumption by converting data signals of n-bit code constitution to data signals of (n+1)-bit code constitution and using specific (n+1)-bit code which is not used as code for data for a frame synchronizing signal.
CONSTITUTION: An nB(n+1)B-code converting circuit 2 is provided, and input signals 1 of n-bit data are converted to (n+1)-bit code in a data converting section 3 and a frame signal 6 is added to data signals as a unique word of (n+1)-bit constitution in a unique word preparing section 4. Data signals and frame signal converted in the converting circuit 2 are converted to serial signals by a parallel serial converting circuit 5 and sent out output signals. The data converting section 3 converts data signals to (n+1)-bit code having little continuation of the same code, and the unique word preparing section 4 sends out the unique word instead of data signals when the frame signal 6 is given.
JPS62220037 | PARALLEL SYNCHRONIZING CIRCUIT |
JP2009130796 | METHOD AND DEVICE FOR DIGITAL BROADCAST RECEPTION |
JPS60130244A | 1985-07-11 | |||
JPS5483411A | 1979-07-03 |
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