PURPOSE: To enable to use low speed ICs by taking the time required for the processing longer, by independently making the control of mode selection for code conversion in pulse train in serial-parallel conversion of input data corresponding to each word.

CONSTITUTION: An input data (1) is written in a 4Q bit shift register 11 with a clock signal 2, where Q is the number of words processed in parallel. A 4Q-bit memory 12 produces a parallel output signal (5) to keep it for 4Q-bit. Further, the signals (5) are inputted to a 4B/3T conversion circuits 4-1∼4-Q sequentially in 4 consective words. The output of the circuits 4-1∼4-Q is applied to data selectors 5-1∼5-Q and mode selection is made according to the result of discrimination of discrimination circuits 6-1∼6-Q. A parallel serial conversion circuit 14 produces a pulse (10) at tri-state signal in Q-word and a tri-state forming circuit 10 produces an output consisting of 4B/3T codes.