To provide a code error detection circuit capable of detecting code errors at a high speed.

A CRC code word excluding a fixed pattern 100 is supplied to the code data input terminal 3 of a division circuit 1 synchronized with clock signals clk and divided by the division circuit 1 and the remainder data of the divided result are outputted from output terminals 7(1)-7(32). The remainder data outputted from the output terminals 7(1)-7(32) are compared with a CRC peculiar value to be comparison data in a comparator circuit 8 and compared result signals for indicating whether or not an error is present in the CRC code word are outputted. A temporary storage means 9 fetches the compared result signals corresponding to the rise of the clock signals inputted to a clock signal input terminal T, tentatively stores them and outputs the storage contents through an output node Q as error detection signals.