To reduce a time for division arithmetic for input data which has a characteristic that it includes many continuous 0.

This code generation circuit is provided with a dividing circuit constituted in the form of a shift register by connecting flip flops F1 to F8, selectors 130 to 137 and exclusive OR circuits 110 to 113 in serial, and a division remainder decision circuit 101 comprising a remainder shifting circuit which compares the number of digits of leading 0 of a value on the shift register with that of leading 0 of following input data and outputs a value obtained by shifting the value on the shift register by the skipping number of digits with the smaller number of digits as the skipping number of the digits. When the skip number of digits is 1, a selector circuit selects the output of the remainder shifting circuit. When the skip number of digits is 0, the selector circuit selects the output of a flip flop connected just before each.