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Patent Searching and Data


Title:
CODEC
Document Type and Number:
Japanese Patent JPH04172738
Kind Code:
A
Abstract:

PURPOSE: To relieve the increase in the circuit scale in the case of digital processing by employing a barrel shifter, an adder and an accumulator used repetitively with respect to a latched output of three input registers for a digital arithmetic circuit being a component of an amplifier.

CONSTITUTION: A digital arithmetic circuit 70 consists of a TA register 16 being a 1st temporary latch register, a TC register 17 being a 2nd temporary latch register, and a TB register 18 being a 3rd temporary latch register and has amplifier functions 21-26 and an addition function 27. Thus, after latch outputs of the three input registers are amplified, they are all added to output a 1st output signal, and latch outputs of the 1st input register 16 and the 2nd input register 17 are amplified and any signal is outputted as a 2nd output signal.


Inventors:
MARUYAMA MASAKATSU
SAKIYAMA SHIRO
MICHIMASA SHIRO
NAKAHIRA HIROYUKI
Application Number:
JP30188990A
Publication Date:
June 19, 1992
Filing Date:
November 06, 1990
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04M1/00; H04M1/253; (IPC1-7): H04M1/00
Attorney, Agent or Firm:
Hiroshi Maeda