Title:
符号化装置、復号化装置および方法
Document Type and Number:
Japanese Patent JP3987556
Kind Code:
B2
Abstract:
A synchronisation signal generator (11) gives the clock start signal and a clock generator and synchroniser (12) produces transmission, coding and decoding signals as well as a low frequency clock. The decoder (13) samples during a reception phase. The coder (14) has its XOR-gate between the input signal for coding during the emission phase and the transmission clock. The coder clock is generated from a frequency divider and is synchronised after reception using the first falling edge of the received signal. The decoder clock uses the same divider and has a set delay, sampling the input line at the rising edge of the clock. The clocks may operate at 9600 bauds.
Inventors:
Salman Abu Hassan
Application Number:
JP2006102014A
Publication Date:
October 10, 2007
Filing Date:
April 03, 2006
Export Citation:
Assignee:
FRANCE TELECOM
La Post
La Post
International Classes:
H03M7/12; H03M5/12; H04L25/49
Domestic Patent References:
| JP5175934A | ||||
| JP6177775A | ||||
| JP6123773A | ||||
| JP63139428A | ||||
| JP6011299A | ||||
| JP6069932A | ||||
| JP4259137A | ||||
| JP6021979A | ||||
| JP5122203A | ||||
| JP61113325A | ||||
| JP6096300A | ||||
| JP5083237A | ||||
| JP62290228A |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe