PURPOSE: To operate stably and at high speed at one time or reading out sense data in a memory device.

CONSTITUTION: A bit line B and /B are respectively connected to internal bus lines D and /D via conduction control gates 6-1 and 6-2, 6-3 and 6-4, column selecting gates 5-1, 5-2. A pre-charge voltage VBP is inputted to the conduction control gates. Pre-charge voltage VBP is intermediate potential between high and low potential, and bit lines B, /B and internal bus lines D, /D are kept at VBP. Thereby, when difference of potential of bit lines at the time of amplification gets larger, since bit lines and internal bus lines are made conduction, timewise margin can be omitted. Also, even if column selecting is early performed, since bit lines and internal bus lines are non-conduction state, stable amplifying operation is secured independently of internal bus. Further, since difference of potential between the bit line B and /B is not reduced and capability of a sense amplifier can be secured, reading out at high speed can be realized.