PURPOSE: To decrease a peak current without decreasing operation speed by operating only a sense amplifier of a bit line connected to a data line at high speed and operating the other sense amplifiers at low speed, in a memory.
CONSTITUTION: When bit lines BLO and /BLO are accessed, a sense amplifier 1 is operated at high speed making gates 4, 5, 18, 19 an ON state, and sense amplifiers 2, 3 are operated at low speed making gates 7, 9, 21, 23 of the other sense amplifiers an OFF state. Thereby, even if many sense amplifiers simultaneously operate accompanying increasing memory capacity, since a peak current can be decreased without slowing access time while access time can be shortened without increasing a peak current, it is useful for increasing memory capacity.
WO/2001/046959 | A MULTI-LEVEL, LOW VOLTAGE SWING SENSING SCHEME FOR HIGH SPEED MEMORY DESIGN |
JP4514380 | Semiconductor memory device |
JPS59168990 | VOLTAGE SENSING CIRCUIT |
MORI TOSHIKI