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Patent Searching and Data


Title:
COMBINED CIRCUIT COMPOSED OF DIGITAL PHASE COMPARATOR WITH ZERO-DEBT BAND AND MINIMUM OFFSET AND CHARGE PUMP
Document Type and Number:
Japanese Patent JPS6469122
Kind Code:
A
Abstract:
PURPOSE: To eliminate the phase comparison dead band of a digital phase locked loop(PLL) by resetting a comparator through the function of a charge pump having both the functions of charging and discharging. CONSTITUTION: High-speed charging/discharging operation is performed inside a charge pump 15, a means for detecting the time when simultaneously executing both the functions of charging and discharging is provided, and the charge pump 15 is connected to a power source, the injection current source of a low- pass filter(LPF) and voltage controlled oscillator(VCO) coupling to be used for the PLL. Besides, since a digital phase detector 11 has a reset terminal for responding to the simultaneous charging/discharging operation of the charge pump 15, two kinds of charge pump operation appear before resetting is generated, and any delay element is not required. When increasing the frequency of a VCO, the up output of a phase comparator is made superior and the charge pump 15 injects a current into the LPF. When decreasing the frequency of the VCO, the down output of the phase comparator is made dominant, and the charge pump pulls a current out of the LPF. Thus, the dead band is removed.

Inventors:
DEEBUITSUDO EI BAIAADO
GEERII DABURIYUU TEIITSU
KUREIGU EMU DEIBUISU
Application Number:
JP20454088A
Publication Date:
March 15, 1989
Filing Date:
August 17, 1988
Export Citation:
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Assignee:
NATL SEMICONDUCTOR CORP
International Classes:
H03L7/085; G01R25/00; H03L7/089; (IPC1-7): H03L7/08