PURPOSE: To shorten the inspection time by a method wherein input terminals for inspection are provided so that a part of frequency dividing flip-flops are unnecessitated at the inspection of the circuit by the instructions given by the input terminals.
CONSTITUTION: At least a part of the group of frequency dividing flip-flops for timing a first time clearing signal and a part of the group of frequency dividing flip-flops for timing a second time clearing signal constitute the common group of frequency dividing flip-flops of a timer 16. In addition, the input terminals 21W 29, which give instructions from outside to the first logic circuit of a control circuit 17. The first logic circuit is provided so that clock pulses to be inputted in some frequency dividing flip-flops in the common group of frequency dividing flip-flop bypasses said some frequency dividing flip-flops when the voltages of the input terminals are at the levels of the one group. At the same time, the first logic circuit is provided so as to frequency-divide said some frequency dividing flip-flops also when the voltages of the input terminals are at the levels of the other group.
MIYANAKA MOTOSHI
HAYATA YOSHIKI
| JPS55118528A | 1980-09-11 | |||
| JPS56102613A | 1981-08-17 | |||
| JPS50161149A | 1975-12-26 |
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