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Patent Searching and Data


Title:
COMMAND DECODE SYSTEM IN INPUT AND OUTPUT CONTROL UNIT
Document Type and Number:
Japanese Patent JPS5619133
Kind Code:
A
Abstract:

PURPOSE: To locate the head address of program corresponding to the command to an arbitrary memory area, by reducing the memory area required for the command decoding and locating the decoding constant to an arbitrary area of memory at a bundle.

CONSTITUTION: The tab information from the instruction processor to the basic peripheral adaptor BPA (input and output unit) is set to the ITAG register 7 of the interface section 1, and the tab information from BPA to the processor is set to the BTAG register 8. Further, the data bus is taken bidirectional and the data between the processor and BPA is set to the data register 9. Further, the write data from the processor is set to RAM5 and the data is delivered to the write-in data register 18 and the driver 11 of the line control section 4 to BPA. Further, in case of read, the read data from BPA is set to the read line data register 17 through the receiver 10 and the data from the register 17 is stored in RAM5, and it is delivered to the processor.


Inventors:
MORIOKA SHIGEYUKI
KAWAKATSU KUNIHIRO
MATSUDA TOSHIHARU
Application Number:
JP9436679A
Publication Date:
February 23, 1981
Filing Date:
July 25, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/10; G06F3/00; G06F9/30; (IPC1-7): G06F3/00; G06F9/30