Title:
COMMON BUS INPUT/OUTPUT CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPH06161933
Kind Code:
A
Abstract:
PURPOSE: To provide a common bus input/output control system which never recognizes a DMA operation fault even when a channel clear signal is generated.
CONSTITUTION: In an I/O controller 10 which controls the transfer of data between a main memory 2 and an input/output device 20, a controller 10 which contains an MPU 12 which controls the input/output control of data, a DMA circuit 11 which controls the DMA transfer of data between the memory 2 and the device 20, a DMA circuit control part 14 which performs the control so that the circuit 11 interrupts the DMA operation after the DMA cycle is complete when a channel clear signal is received from a CPU 1 are provided.
Inventors:
OUCHIDA HIROSHI
MASUDA HIROKI
MASUDA HIROKI
Application Number:
JP31171892A
Publication Date:
June 10, 1994
Filing Date:
November 20, 1992
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F13/12; G06F13/28; (IPC1-7): G06F13/12; G06F13/28
Attorney, Agent or Firm:
Fujishima Ijima (1 outside)
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