PURPOSE: To improve speed for communication while keeping the high speed for frame processing by providing a competition circuit equipped with an access control function and a guarantee function in the peripheral circuit of a frame memory.

CONSTITUTION: In the peripheral circuit of a frame memory 31, a competition circuit 19 is provided with the access control function to control the read of a data from the frame memory 31 by monitoring a control signal showing the condition of access from a control processor to the frame memory, and the storage guarantee function to guarantee the buffering of the frame memory 31 by counting the control signal and limiting the memory access of the control processor when the count value exceeds a prescribed value. Therefore, the control processor enable arbitrary access to the frame memory 31 and even on the side of the frame processing, the time for buffering to the frame memory 31 is guaranteed. Thus, the speed for communication is improved while keeping the high speed for frame processing.