Title:
COMMUNICATION CONTROL SYSTEM BETWEEN PROCESSORS
Document Type and Number:
Japanese Patent JPS60258669
Kind Code:
A
Abstract:
PURPOSE:To attain direct access to main control processor for the communication area of the memory of a sub ordinate control processor by sending a request for communication from the main control processor and placing the subordinate control processor in a termporary stop state. CONSTITUTION:The main control processor MPU sends communication request information to the subordinate control processor SPU1. The subrodinate control processor SPU1 sends communication ready information to an information line m1 and holds itself in a temporary suspending stop state. The communication ready information of the information line m1 opens a bus gate BG1 corresponding to the subordinate control processor SPU1. Consequently, the main control processor MPU attains direct access to the memory M1 of the subordinate control processor SPU1. When the communication ready information of the information line m1 is ceased, the bus gate BG1 is closed and the communication ready information of the information line l1 is also ceased. Thus, communication control over all subordinate control processors SPU1-SPUn is performed.
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Inventors:
TOMINAGA YOSHINOBU
HOUJIYOU KATSUO
SHIGETA YUKIO
KOBAYASHI HANJI
HOUJIYOU KATSUO
SHIGETA YUKIO
KOBAYASHI HANJI
Application Number:
JP11581884A
Publication Date:
December 20, 1985
Filing Date:
June 06, 1984
Export Citation:
Assignee:
MEISEI ELECTRIC CO LTD
International Classes:
H04Q3/545; G06F13/28; G06F13/38; G06F15/16; G06F15/17; G06F15/177; (IPC1-7): G06F13/38; G06F15/16
Domestic Patent References:
| JPS5864528A | 1983-04-16 |
Attorney, Agent or Firm:
Teruo Taniyama