To provide a communication semiconductor integrated circuit (high frequency IC) which incorporates a receiving circuit capable of correcting variations in filter characteristics of a high-gain amplifier circuit through calibration even if the filter characteristics are varied by a manufacturing process.
In the communication semiconductor integrated circuit (high frequency IC) which incorporates a serial signal processing circuit (high-gain amplifier circuit 220) configured by cascade-connecting in series a plurality of low-pass filters (LPFs) and variable gain amplifier circuits (PGAs), as capacitance of the low-pass filters constituting the serial signal processing circuit, a variable capacitance circuit comprised of a plurality of capacitance elements and switch elements connected in series with these capacitance elements, respectively is provided and at start up, a reference clock signal is applied to the circuit including the low-pass filters to determine how much a delay time of the circuit is deviated from a design value. The ON/OFF state of each of the switch elements in the variable capacitance circuit is then set to minimize the deviation of the delay time.
OKAZAKI TAKAO
SENDA SAKAE
SHIMA YASUO
SMITH GARY
| JP2005020119A | 2005-01-20 | |||
| JP2002280839A | 2002-09-27 |