PURPOSE: To decrease a circuit scale and the cost and to relieve a load to a hardware by reading a data at a prescribed address with a transmission data address signal, transmitting the data read from a data memory with a transmission timing signal and transmitting a reception data with a delay.

CONSTITUTION: The transmission data address signal E forms an address An+k storing the k-th word of a reception signal when the output D of a transmission frame counter is Ak. The transmission data address signal E is subjected to time division processing by a 3-state buffer 51, the result is inputted to the data memory 10 to read the transmission data of a designated address. The transmission data read from the data memory 10 is loaded in parallel in a parallel/serial converting shift register 60, where the result is shifted by using a transmission bit clock and the parallel/serial conversion shift register output is obtained. Then the result is subjected to code modulation by a line driver 61 and a transmission data is outputted to a transmission line by using the transmission timing signal from a clock generator 40.