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Title:
COMPARATOR OF BINARY SIGNAL AND PLL CIRCUIT USING IT
Document Type and Number:
Japanese Patent JP2001021596
Kind Code:
A
Abstract:

To make detectable a phase difference between two input signals by counting a second input signal by a counter reset for every change in a first input signal and outputting a digital value according to the frequency ratio of the two input signals.

When the frequency of a first input signal 111, the frequency of a second input signal 112, and a frequency ratio set value 116 are set to f1, f2, and (m) respectively, an integrator 108 provides mxf1 signal obtained by multiplying the frequency of the first input signal 111 by (m) times and a digital value 118 expressing a phase difference from the second input signal 112. In this case, (m) is not restricted to integer but may be a decimal. Therefore, even if the frequency ratio f1/f2 of the two input signals 111, 112 is any value, the phase of the two signals can be compared. This constitution can detect the frequency ratio of the two input signals of different frequencies and detect an error between the frequency ratio and the frequency ratio set value.


Inventors:
YASUDA AKIRA
Application Number:
JP19760999A
Publication Date:
January 26, 2001
Filing Date:
July 12, 1999
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G01R23/10; G01R25/00; H03D13/00; H03K5/26; H03L7/06; H03L7/085; (IPC1-7): G01R23/10; G01R25/00; H03D13/00; H03K5/26; H03L7/06; H03L7/085
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)