Title:
COMPARATOR CIRCUIT
Document Type and Number:
Japanese Patent JPH02272907
Kind Code:
A
Abstract:
PURPOSE: To prevent frequent occurrence of an error signal by generating a 'anticoincidence' signal only when it is detected that both binary circuits are stable but their states differ for a minimum period and masking the 'anticoincidence' signal in other cases. CONSTITUTION: Two binary signals a, b are compared, the signal (a) is received at an input terminal 40, and the signal (b) is received by an input terminal 44. When either of the two signals a, b is zero, that is, only when the signals a, b are stable at least for a critical period and they differ from each other, a NAND gate 52 produces logical '1', that is, a 'anticoincidence' signal and masks the 'anticoincidence' signal in other cases. Since the dissidence for a short time is masked in this way, an excess error signal given frequency is avoided.
Inventors:
FUREDERIKASU HENRIKASU YOSEFU
Application Number:
JP5387190A
Publication Date:
November 07, 1990
Filing Date:
March 07, 1990
Export Citation:
Assignee:
PHILIPS NV
International Classes:
H03K5/26; G06F7/02; G06F11/16; (IPC1-7): H03K5/26
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)