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Title:
COMPENSATION OPTIMIZING METHOD FOR DISTORTION COMPENSATION AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JP2001024449
Kind Code:
A
Abstract:

To shorten the time for detecting the optimal value of distortion compensating amounts in a feedfoward distortion compensation amplifier circuit which commonly amplifies a multi-frequency signal and is used for a base station and a relay system.

In this method for obtaining an optimal point from the value of a detection signal extracted from each distortion detecting loop and distortion removing loop as a control signal to be applied from a control circuit to each vector adjuster of the distortion detecting loop and the distortion removing loop, at first, the detection value of an arbitrary detection point (2000) in the adjustment range of each vector adjuster is read, and detection values before and after the detecting point obtained by sequentially adding a certain number (225) to the detection value are sequentially compared, and when the sizes of the detection values before and after the detecting point are inverted, a smaller number than the certain number is added to the detection value of the previous detecting point, and the detection values are sequentially compared in the same way. When the three detection values are continuously made almost equal, the central detecting point is judged as an optimal point.


Inventors:
SHIMADA NOBUYASU
Application Number:
JP2000190802A
Publication Date:
January 26, 2001
Filing Date:
August 10, 1994
Export Citation:
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Assignee:
HITACHI INT ELECTRIC INC
International Classes:
H03F1/32; H03F3/24; (IPC1-7): H03F1/32; H03F3/24
Attorney, Agent or Firm:
Otsuka Manabu