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Patent Searching and Data


Title:
COMPILE PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPH04155576
Kind Code:
A
Abstract:

PURPOSE: To efficiently combine a vector arithmetic and a parallel execution by a loop slice, to improve an execution efficiency, and to shorten an executing time by executing the loop slice to a VL loop as a unit of PVL by a cyclic distribution system.

CONSTITUTION: A compiler 1 translates a source program 9, and generates an object program 10 including the parallel execution part of the vector arithmetic. A loop detecting part 5 detects a loop included in the source program 9, and a vectoring part 6 generates the vector arithmetic from the detected loop. A VL loop forming part 7 generates the VL loop about the generated vector arithmetic, and a VL loop slice part 8 executes the loop slice to each VL loop as the unit of a vector length (a physical vector length;PVL) at the execution by the cyclic distribution system. When executing the object program generated by the above processes after an executionable form, as the result of the loop slice, the PVL is parallel executed. Thus, it is possible to reduce the influence of a synchronizing process, to improve the efficiency of the parallel execution, and to shorten the executing time.


Inventors:
NOZAKI HIDEKI
HOTTA KOICHIRO
NAGAKURA HIROSHI
YAMANAKA EIJI
Application Number:
JP28138990A
Publication Date:
May 28, 1992
Filing Date:
October 19, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F15/16; G06F9/45; G06F17/16; (IPC1-7): G06F9/45; G06F15/16; G06F15/347
Domestic Patent References:
JPH01113867A1989-05-02
JPH0298741A1990-04-11
Attorney, Agent or Firm:
Hiroshi Morita (2 outside)