Title:
COMPLEMENTARY CIRCUIT
Document Type and Number:
Japanese Patent JPS54152479
Kind Code:
A
Abstract:
PURPOSE: To miniaturize a chip by making connection between transistors on p and n-type semiconductors of a complementary circuit via a connection hole extending to both semiconductors.
CONSTITUTION: A poly Si layer (indicated by oblique broken lines) is formed spreading over both p-channel FET formation region 11 and n-channel FET formation region 14. For region 11, p-type poly Si is used and for region 14, n-type poly Si is used. Connection hole 20 is provided extending over both regions and both Si regions are connected together via metal. Consequently, troublbe such as pn junction between regions 11 and 14 is eliminated and no dead space is formed, so that the chip can be miniaturized.
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Inventors:
SUZUKI YASOJI
OCHII KIYOBUMI
OCHII KIYOBUMI
Application Number:
JP5998278A
Publication Date:
November 30, 1979
Filing Date:
May 22, 1978
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Domestic Patent References:
| JPS49112574A | 1974-10-26 | |||
| JPS50105283A | 1975-08-19 |
Foreign References:
| US3673471A | 1972-06-27 |