PURPOSE: To decrease the scale of titled circuit and to quicken the operating speed by using an inverter receiving the control of an output control signal to allow an output circuit to bring the state into gate open or gate closing with high impedance.
CONSTITUTION: When an output control terminal 22 is logical L, transistors (Trs) 4p, 4n form a transmission gate of complementary MOSTr type. Trs 3p, 3n form an inverter and also Trs 1p, 1n form an inverter. Thus, the circuit takes a form that two stages of inverters are connected between an input terminal 20 and an output terminal 21 and the logical state of the input terminal 20 appears as it is at the output terminal 21. When the level of the output control terminal 22 is logical H, since the transmission gate comprising the Trs 4p, 4n is turned off, the Trs 3p, 3n do not constitute an inverter, but the Trs 2p, 2n are turned off, then the Trs 1p, 1n remark turned off. Thus, the transmission of signal from the input terminal 20 to the output terminal 21 is inhibited and the level of the output terminal 21 is kept in high impedance.
SHICHINOHE DAISUKE
HONGO KATSUNOBU
| JPS5575349A | 1980-06-06 | |||
| JPS55141825A | 1980-11-06 |