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Title:
COMPLEMENTARY SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5851325
Kind Code:
A
Abstract:

PURPOSE: To improve the package efficiency and to reduce power consumption by adding circuits which freely selectively switch the supply of clock signals to plural functional packaged on one semiconductor integrated circuit device.

CONSTITUTION: Circuit blocks 4W6 are divided by functions are each have a clock input terminal CLK, and gate circuits 21W23 supply clocks to their clock input terminals selectively. Then, control circuits 17W20 receive an external signal and control the selective clock supplying operation of the gate circuits 21W23. For example, write information is supplied to registers 18W20 for clock supply information storage through input terminals 11W13, and write pulses at that time are generated by decoding the combination of the terminals 14W16 through a decoder 17 and then supplied as strobe pulses to the registers 18W20 to store the clock supply information. Then, no clock is supplied to the unused blocks 5 and 6.


Inventors:
NAKAGAWA JIYUNICHI
MIZUKAMI MASAO
SUZUKI TOORU
Application Number:
JP14946481A
Publication Date:
March 26, 1983
Filing Date:
September 24, 1981
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
H03K19/0948; G06F1/04; (IPC1-7): H03K19/094
Attorney, Agent or Firm:
Toshiyuki Usuda



 
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