Title:
COMPLEMENTARY TYPE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH01181317
Kind Code:
A
Abstract:
PURPOSE:To decrease the forming area of an input gate protection circuit without increasing the manufacture process of a semiconductor device by using a channel of an isolation gate field effect transistor (IC-FET) for a resistor of the input gate protection circuit. CONSTITUTION:A resistor R formed by a channel formed under the gate by connecting a gate of an enhancement N-channel IG-FETQ1 provided between an input terminal IN and an output OUT of the input gate protection circuit to a VDD is used as the resistor of the input gate protection circuit. The resistance of the resistor R is set optionally by varying the channel length and the channel width of the enhancement type N-channel IG-FETQ1. Thus, the forming area of an input gate protection circuit is decreased without increasing the manufacture process of a semiconductor device.
Inventors:
ITOMI NOBORU
Application Number:
JP590888A
Publication Date:
July 19, 1989
Filing Date:
January 14, 1988
Export Citation:
Assignee:
SEIKO EPSON CORP
International Classes:
H03K19/003; H03K17/08; H03K19/094; H03K19/0948; (IPC1-7): H03K17/08; H03K19/003; H03K19/094
Attorney, Agent or Firm:
Mogami (1 person outside)